OPEN TO OPPORTUNITIES · SOHAG, EGYPT

Abdallah Mohammed
Abdelqader

Communications & Electronics Engineer — Digital IC Design Specialist

abqader2003@gmail.com / +20 106 307 0388 / linkedin.com/in/abdallah-abdelqader-engineer

Degree Grade

Very Good with Honors

Graduation Project

Excellent

IC Design Diploma

Excellent (97%)

U0 About

A newly graduated Communications & Electronics Engineer from Sohag University, majoring in electrical engineering with a focus on Digital IC Design — the discipline of turning circuit ideas into silicon, from Verilog RTL all the way to a GDSII layout. Graduated with Very Good with Honors, and earned an Excellent grade in both the final year and the graduation project. Also builds Python-based automation tools and AI-assisted software on the side.

U1 Education ACADEMIC RECORD

B.Sc. in Communications & Electronics Engineering 2021 — 2026

Faculty of Engineering, Sohag University · Sohag, Egypt

Overall grade: Very Good with Honors
Final year grade: Excellent (GPA 3.02)
Graduation project grade: Excellent

Egyptian General Secondary Certificate — Mathematics Stream 2018 — 2021

Martyr Abdel Moneim Riyad Secondary School · Sohag, Egypt

Final score: 87.9%
Ranked 3rd on the school level

U2 Graduation Project 2026 · GRADE: EXCELLENT

Accelerating Polynomial Arithmetic for Post-Quantum Cryptography on Vortex GPGPU

Designed and implemented optimized Number Theoretic Transform (NTT), modular arithmetic, and polynomial multiplication hardware architectures for Kyber ML-KEM in Verilog HDL.
Targeted deployment on the Vortex GPGPU platform to accelerate core Post-Quantum Cryptography (PQC) arithmetic — bridging quantum-resistant security with high-performance hardware acceleration.
Successfully defended the project before the department's evaluation committee.

Supervisors: Dr. Ahmed Farghal · Dr. Hossam Hassan · Eng. Mohamed Yosri
Team lead: Moaz Ismail · Team: Kerolos, Mostafa, Ramez, Mena

U3 Professional Development JUL — SEP 2025

Full Digital IC Design Diploma Excellent · 97%

Under the supervision of Eng. Ali El-Temsah

End-to-end ASIC program: RTL coding in Verilog, self-checking testbenches, TCL scripting, Static Timing Analysis, low-power design, Clock Domain Crossing, RTL synthesis, DFT insertion, formal verification, and full physical implementation to sign-off.
Capstone: RTL-to-GDSII implementation of a low-power configurable multi-clock digital system — receiving commands over UART, processing through an ALU and register file, and transmitting results through an asynchronous FIFO across clock domains.
Designed system blocks from scratch: ALU, register file, synchronous FIFO, clock divider, clock gating, synchronizers, main controller, UART TX/RX — then synthesized, timing-closed, formally verified, and carried through place-and-route to a final GDSII.

U4 Skills SIGNAL STRENGTH = PROFICIENCY

Digital IC Design

Verilog RTL & Testbenches

Static Timing Analysis

Clock Domain Crossing

Low-Power Design

Design for Testing (DFT)

TCL Scripting

Programming & Automation

Python

Personal Skills

U5 Projects SIDE BUILDS

Ayat Maker

Cross-platform Python automation utility for professional video generation, supporting Windows and Linux (Ubuntu).

github.com/ABQADER2003edu/ayatmaker →

Samsung TV Controller

Custom FlutterFlow integration for remote control of Samsung Smart TVs.

Financial Verification Bot

Python-based system for real-time payment tracking and automated confirmation.

U6 Certifications & Courses

Full Digital IC Design Diploma — Excellent (97%)2025

IBM Applied Data Science Specialization — Coursera (Next Coders)80 hrs · 2019–20

AI Programming with Python — Udacity (Next Coders)52 hrs · 2019–20

Connect: Intro to Programming — Udacity (Next Coders)109 hrs · 2019–20

Digital Marketing Challenger — Udacity2 months · 2021

Communication Package — Telecom Egypt (We)4 weeks · 2024

U7 Languages

ARABIC — Native

ENGLISH — Good